A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects

Photonic devices fabricated with back-end compatible silicon pho-tonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to sig-nificantly enhance photonic network-on-chip (PNoC) architecture performance. In this paper, we present a detailed comparative analy-sis of a number of design tradeoffs for CMOS front-end and back-end compatible devices for silicon photonic interconnects. A cross-layer optimization of multiple device-level and link-level design pa-rameters is performed to enable the design of energy-efficient on-chip photonic interconnects using BCSP devices. The optimized design of BCSP on-chip links renders more energy-efficiency and aggregate bandwidth than FCSP on-chip links, in spite of the inferior opto-elec-tronic properties of BCSP devices. Our experimental analysis com-pares the use of BCSP and FCSP links at the architecture level, and shows that the optimized design of the BCSP-based Firefly PNoC achieves 1.15x greater throughput and 12.4% less energy-per-bit on average than the optimized design of FCSP-based Firefly PNoC. Similarly, the optimized design of the BCSP-based Corona PNoC achieves 3.5x greater throughput and 39.5% less energy-per-bit on average than the optimized design of FCSP-based Corona PNoC.