一种专门用于软计算的并行架构框架

Proceedings Eleventh International Conference on VLSI Design Pub Date : 1998-01-04 DOI:10.1109/ICVD.1998.646625

G. Ascia, V. Catania

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引用次数: 4

摘要

本文介绍了一种用于实时模糊应用的并行处理器体系结构。该体系结构的主要特点是:具有模糊输入的前词的正真度的预计算阶段;活动规则的检测阶段。处理速度高达2.8 MFLIPS(256条规则，8个前因式，1个后因式)。硅面积估计为25mm /sup /。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A framework for a parallel architecture dedicated to soft computing

This paper presents the architecture of a parallel processor dedicated to real-time fuzzy application. The main features of the architecture are: a pre-computation phase of the positive degree of truth of the antecedent with fuzzy inputs; a detection phase of the active rules. The processing speed is up to 2.8 MFLIPS (256 Rules, 8 Antecedents, 1 Consequent). The silicon area estimated is 25 mm/sup 2/.

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Proceedings Eleventh International Conference on VLSI Design

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