Yizhou Zhang, Zheng Zhou, Peng Huang, Mengqi Fan, Runze Han, W. Shen, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang
{"title":"基于1T1R阵列的正向/反向传播模块二进制神经网络硬件加速结构改进","authors":"Yizhou Zhang, Zheng Zhou, Peng Huang, Mengqi Fan, Runze Han, W. Shen, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang","doi":"10.23919/SNW.2019.8782967","DOIUrl":null,"url":null,"abstract":"An improved hardware acceleration architecture of RRAM based Binary Neural Networks (BNNs) is proposed and demonstrated. In the architecture, a 1T1R array-based propagation module is introduced and designed to realize the computing acceleration of fully parallel Vector-Matrix Multiplication (VMM) in both forward and backward propagation. By using the propagation module, high acceleration is achieved in both training (50×) and inference (273×) process.","PeriodicalId":170513,"journal":{"name":"2019 Silicon Nanoelectronics Workshop (SNW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An Improved Hardware Accelaration Architecture of Binary Neural Network With 1T1R Array Based Forward/Backward Propagation Module\",\"authors\":\"Yizhou Zhang, Zheng Zhou, Peng Huang, Mengqi Fan, Runze Han, W. Shen, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang\",\"doi\":\"10.23919/SNW.2019.8782967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An improved hardware acceleration architecture of RRAM based Binary Neural Networks (BNNs) is proposed and demonstrated. In the architecture, a 1T1R array-based propagation module is introduced and designed to realize the computing acceleration of fully parallel Vector-Matrix Multiplication (VMM) in both forward and backward propagation. By using the propagation module, high acceleration is achieved in both training (50×) and inference (273×) process.\",\"PeriodicalId\":170513,\"journal\":{\"name\":\"2019 Silicon Nanoelectronics Workshop (SNW)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/SNW.2019.8782967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2019.8782967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Improved Hardware Accelaration Architecture of Binary Neural Network With 1T1R Array Based Forward/Backward Propagation Module
An improved hardware acceleration architecture of RRAM based Binary Neural Networks (BNNs) is proposed and demonstrated. In the architecture, a 1T1R array-based propagation module is introduced and designed to realize the computing acceleration of fully parallel Vector-Matrix Multiplication (VMM) in both forward and backward propagation. By using the propagation module, high acceleration is achieved in both training (50×) and inference (273×) process.