A Novel Migration Technique to Balance Thermal Distribution for Future Heterogeneous 3D Chip Multiprocessors

The industry trend of Chip Multiprocessors (CMPs) architecture is to move from 2D CMPs to 3D CMPs architecture which obtains higher performance, more reliability, reduced cache access latency, and increased cache bandwidth. Moreover, 3D CMP architectures have recently gained significant attention to tackle the increasing power consumption in single core processors. However, one key challenge in designing the 3D CMP is the thermal issue as a result of maximizing the throughput. The thermal hotspot causes performance degradation and reliability reduction in the 3D CMP. In this paper, a run-time task migration approach is proposed to balance the temperature and reduce the number of hotspots in the 3D CMP without any performance degradation. The proposed approach is divided into two algorithms that aim at maximizing the throughput on the 3D CMP while satisfying the peak temperature constraint. Experimental results on the PARSEC benchmarks show that the proposed architecture yields up to 60 % reduction in overall chip energy with just 17 % performance degradation on average over all the used workloads. The best energy saving was 72 % with a negligible performance degradation.