Reduced complexity FPGA implementation for UF-OFDM frequency domain transmitter

Universal Filtered Orthogonal Frequency Division Multiplexing (UF-OFDM) is considered one of the main wave-form candidates to overcome the challenges facing the next generation of mobile communication systems. Due to its spectral properties it can support relaxed synchronization, low-latency communications and flexible time transmission interval. Nevertheless, the available recent literature addresses the potential of this waveform mainly from communication performance perspective, and sometimes presents a rough estimation of the complexity. Therefore, it becomes high of interest to seek efficient hardware implementations. In this paper, a reduced complexity pipelined architecture is proposed for UF-OFDM frequency domain transmitter. Using LTE parameters, the proposed UF-OFDM FDA architecture uses around 3.6 times less hardware ressources than the straightforward implementation.