25/50MHz双模并行乘法器/累加器

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156650

F. Welten, J. Lohstroh, A. Linssen

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引用次数: 0

摘要

采用标准3μm双极氧化物隔离ISL技术的12 × 12并联倍增器/蓄电池将被描述。可以绕过的门控管道寄存器允许芯片以25MHz的速率在直接模式下或以50MHz的时钟速率在管道模式下使用。功耗900mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 25/50MHz dual-mode parallel multiplier/accumulator

A 12 × 12 parallel multiplier/accumulator using standard 3μm bipolar oxide-isolated ISL technology will be described. A gated pipeline-register which can be bypassed allows the chip to be used in a direct mode at a 25MHz rate or in a pipeline mode at a 50MHz clock rate. Power dissipation is 900mW.

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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