{"title":"FPGA功率评估的灵敏度","authors":"K. K. Poon, S. Wilton","doi":"10.1109/FPT.2002.1188730","DOIUrl":null,"url":null,"abstract":"Power dissipation is becoming a major concern among FPGA vendors. Recently, architectural studies have been published which attempt to quantify the effects of various architectural alternatives on the power dissipation of FPGAs. These studies are very sensitive to assumptions made during the experimentation. In this paper, we analyze the sensitivity of two of these assumptions: the primary input density and the routing algorithm. We show that both of these assumptions significantly impact the architectural results.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Sensitivity of FPGA power evaluation\",\"authors\":\"K. K. Poon, S. Wilton\",\"doi\":\"10.1109/FPT.2002.1188730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Power dissipation is becoming a major concern among FPGA vendors. Recently, architectural studies have been published which attempt to quantify the effects of various architectural alternatives on the power dissipation of FPGAs. These studies are very sensitive to assumptions made during the experimentation. In this paper, we analyze the sensitivity of two of these assumptions: the primary input density and the routing algorithm. We show that both of these assumptions significantly impact the architectural results.\",\"PeriodicalId\":355740,\"journal\":{\"name\":\"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPT.2002.1188730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPT.2002.1188730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

功耗正成为FPGA厂商关注的主要问题。最近,一些建筑学研究已经发表,试图量化各种架构选择对fpga功耗的影响。这些研究对实验过程中的假设非常敏感。在本文中,我们分析了这两个假设的敏感性:主输入密度和路由算法。我们展示了这两种假设对体系结构的结果都有显著的影响。
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Sensitivity of FPGA power evaluation
Power dissipation is becoming a major concern among FPGA vendors. Recently, architectural studies have been published which attempt to quantify the effects of various architectural alternatives on the power dissipation of FPGAs. These studies are very sensitive to assumptions made during the experimentation. In this paper, we analyze the sensitivity of two of these assumptions: the primary input density and the routing algorithm. We show that both of these assumptions significantly impact the architectural results.
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