Bappaditya Mondal, Chandan Bandyopadhyay, H. Rahaman
{"title":"可逆电路外观故障的检测与定位","authors":"Bappaditya Mondal, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1109/ISED.2017.8303946","DOIUrl":null,"url":null,"abstract":"This work presents a testing scheme for detection of two new type of faults (gate appearance and control appearance fault) in reversible circuit. The testing scheme not only efficiently detects the specified faults with minimum number of test vectors but localizes it simultaneously. Our developed approach only requires a single test vector to detect gate appearance fault while to find control appearance fault it needs n test vectors, where n is the number of input lines present in the circuit. The proposed technique can also work for very large circuits as well. In way to verify logical correctness of our developed technique, we have successfully tested different types of benchmark circuits over our proposed algorithms and obtained results are given at the end of this work.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Detection and localization of appearance faults in reversible circuits\",\"authors\":\"Bappaditya Mondal, Chandan Bandyopadhyay, H. Rahaman\",\"doi\":\"10.1109/ISED.2017.8303946\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a testing scheme for detection of two new type of faults (gate appearance and control appearance fault) in reversible circuit. The testing scheme not only efficiently detects the specified faults with minimum number of test vectors but localizes it simultaneously. Our developed approach only requires a single test vector to detect gate appearance fault while to find control appearance fault it needs n test vectors, where n is the number of input lines present in the circuit. The proposed technique can also work for very large circuits as well. In way to verify logical correctness of our developed technique, we have successfully tested different types of benchmark circuits over our proposed algorithms and obtained results are given at the end of this work.\",\"PeriodicalId\":147019,\"journal\":{\"name\":\"2017 7th International Symposium on Embedded Computing and System Design (ISED)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 7th International Symposium on Embedded Computing and System Design (ISED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISED.2017.8303946\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2017.8303946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Detection and localization of appearance faults in reversible circuits
This work presents a testing scheme for detection of two new type of faults (gate appearance and control appearance fault) in reversible circuit. The testing scheme not only efficiently detects the specified faults with minimum number of test vectors but localizes it simultaneously. Our developed approach only requires a single test vector to detect gate appearance fault while to find control appearance fault it needs n test vectors, where n is the number of input lines present in the circuit. The proposed technique can also work for very large circuits as well. In way to verify logical correctness of our developed technique, we have successfully tested different types of benchmark circuits over our proposed algorithms and obtained results are given at the end of this work.