{"title":"低功耗浮点累加器","authors":"R. Pillai, D. Al-Khalili, A. Al-Khalili","doi":"10.1109/ICVD.1998.646628","DOIUrl":null,"url":null,"abstract":"In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low power floating point accumulator\",\"authors\":\"R. Pillai, D. Al-Khalili, A. Al-Khalili\",\"doi\":\"10.1109/ICVD.1998.646628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X.\",\"PeriodicalId\":139023,\"journal\":{\"name\":\"Proceedings Eleventh International Conference on VLSI Design\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Eleventh International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1998.646628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1998.646628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X.
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