使用量化神经元的数字神经处理器

H. Nakahira, S. Sakiyama, M. Maruyama, K. Hasegawa, T. Kouda, S. Maruno, Y. Shimeki, T. Satonaka, Y. Nagano
{"title":"使用量化神经元的数字神经处理器","authors":"H. Nakahira, S. Sakiyama, M. Maruyama, K. Hasegawa, T. Kouda, S. Maruno, Y. Shimeki, T. Satonaka, Y. Nagano","doi":"10.1109/VLSIC.1993.920527","DOIUrl":null,"url":null,"abstract":"We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network calculations. To realize both a large amount of synapses and high speed processing, a neuroprocessor has been fabricated with the Multi-Functional Layered Network (MFLN) model. The neuroprocessor contains 27,000 gates on a chip fabricated by using 1.2 /spl mu/m double metal CMOS, sea of gates technology. Chip size is 10.99 mm x 10.93 mm. The neuroprocessor operates with a clock cycle time of 25 nsec. It simulates the MFLN model with 4,736 neurons and two million synaptic weights in 2.8 msec when the width of the combination function is three. Therefore, the performance is 0.76 GCPS (Giga Connections Per Second). It achieves 20.5 GCPS, when the width of the combination function is one. It can execute Hebbian learning with 20.0 MCUPS (Mega Connections Updated Per Second).","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A digital neuroprocessor using quantizer neurons\",\"authors\":\"H. Nakahira, S. Sakiyama, M. Maruyama, K. Hasegawa, T. Kouda, S. Maruno, Y. Shimeki, T. Satonaka, Y. Nagano\",\"doi\":\"10.1109/VLSIC.1993.920527\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network calculations. To realize both a large amount of synapses and high speed processing, a neuroprocessor has been fabricated with the Multi-Functional Layered Network (MFLN) model. The neuroprocessor contains 27,000 gates on a chip fabricated by using 1.2 /spl mu/m double metal CMOS, sea of gates technology. Chip size is 10.99 mm x 10.93 mm. The neuroprocessor operates with a clock cycle time of 25 nsec. It simulates the MFLN model with 4,736 neurons and two million synaptic weights in 2.8 msec when the width of the combination function is three. Therefore, the performance is 0.76 GCPS (Giga Connections Per Second). It achieves 20.5 GCPS, when the width of the combination function is one. It can execute Hebbian learning with 20.0 MCUPS (Mega Connections Updated Per Second).\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920527\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

我们讨论了一种使用量化神经元的数字神经处理器,用于字符或图像识别和学习。神经网络中突触的数量对图像的准确识别是一个非常重要的因素。具有大量突触的神经网络可以达到较高的识别精度,但由于网络计算量大,使得处理速度降低。为了实现大量突触和高速处理,采用多功能分层网络(MFLN)模型制作了一种神经处理器。该神经处理器采用1.2 /spl μ m双金属CMOS,即栅极海洋技术,在一个芯片上包含27000个栅极。芯片尺寸为10.99 mm × 10.93 mm。神经处理器以25秒的时钟周期运行。在组合函数宽度为3的情况下,以4,736个神经元和200万个突触权重在2.8毫秒内模拟了MFLN模型。因此,性能为0.76 GCPS (Giga Connections Per Second)。当组合函数的宽度为1时,得到20.5 GCPS。它可以以20.0 MCUPS(每秒更新的兆连接)的速度执行Hebbian学习。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A digital neuroprocessor using quantizer neurons
We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network calculations. To realize both a large amount of synapses and high speed processing, a neuroprocessor has been fabricated with the Multi-Functional Layered Network (MFLN) model. The neuroprocessor contains 27,000 gates on a chip fabricated by using 1.2 /spl mu/m double metal CMOS, sea of gates technology. Chip size is 10.99 mm x 10.93 mm. The neuroprocessor operates with a clock cycle time of 25 nsec. It simulates the MFLN model with 4,736 neurons and two million synaptic weights in 2.8 msec when the width of the combination function is three. Therefore, the performance is 0.76 GCPS (Giga Connections Per Second). It achieves 20.5 GCPS, when the width of the combination function is one. It can execute Hebbian learning with 20.0 MCUPS (Mega Connections Updated Per Second).
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Open/folded bit-line arrangement for ultra high-density DRAMs A new very fast pull-in PLL system with anti-pseudo-lock function A 3 V data transceiver chip for dual-mode cellular communication systems A 12.5 ns 16 Mb CMOS SRAM Low voltage mixed analog/digital circuit design for portable equipment
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1