VLSI implementation of a 300-MHz 0.35-/spl mu/m CMOS 32-bit auto-reloadable binary synchronous counter with optimal test overhead delay

We describe the VLSI implementation of a fully testable high-speed binary synchronous counter that is pre-loadable and auto-reloadable. High-speed operation is achieved by precomputing the carry independent terms and by using the carry signal as a selector in the last gate before the storage latch. An efficient test logic is used that has minimal impact on the counter speed during normal operation, and significantly reduces the test time and test cost.