{"title":"嵌入式SRAM的最坏情况设计和余量","authors":"R. Aitken, Sachin Idgunji","doi":"10.1145/1266366.1266648","DOIUrl":null,"url":null,"abstract":"An important aspect of design for yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previously, this has involved multiple simulation corners and extreme test conditions. It is shown that statistical concerns and device variability now require a different approach, based on work in extreme value theory. This method is used to develop a lower-bound for variability-related yield in memories","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"197 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Worst-Case Design and Margin for Embedded SRAM\",\"authors\":\"R. Aitken, Sachin Idgunji\",\"doi\":\"10.1145/1266366.1266648\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An important aspect of design for yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previously, this has involved multiple simulation corners and extreme test conditions. It is shown that statistical concerns and device variability now require a different approach, based on work in extreme value theory. This method is used to develop a lower-bound for variability-related yield in memories\",\"PeriodicalId\":298961,\"journal\":{\"name\":\"2007 Design, Automation & Test in Europe Conference & Exhibition\",\"volume\":\"197 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 Design, Automation & Test in Europe Conference & Exhibition\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1266366.1266648\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Design, Automation & Test in Europe Conference & Exhibition","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1266366.1266648","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An important aspect of design for yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previously, this has involved multiple simulation corners and extreme test conditions. It is shown that statistical concerns and device variability now require a different approach, based on work in extreme value theory. This method is used to develop a lower-bound for variability-related yield in memories