{"title":"结合Matlab与fpga设计并行FIR数字滤波器的案例教学","authors":"Yi Zheng, Ping Zheng","doi":"10.1109/ICAIE50891.2020.00105","DOIUrl":null,"url":null,"abstract":"In order to make undergraduates master a hardware implementation of digital filters, we take the design of a parallel FIR digital low-pass filter as a teaching case, which can present the implementation method of digital filters combining Matlab and a hardware description language together. First, according to the task of the teaching case, the coefficients of FIR digital filter are determined by an FDATool application of Matlab. By normalization and quantization, the filter coefficients and sampled data are both converted from the floating-point data to the fixed-point data. The bit width of valid data bits of FIR filter outputs is determined in accordance with the rule of multiply accumulate operation of FPGAs. Then, we utilize Verilog HDL to implement a fast multiplier and the parallel FIR digital low-pass filter. Finally, we compare the filter outputs of FPGAs with the ones of Matlab, and analyze the reason. The case teaching method, which combines Matlab and FPGAs, is helpful to develop the hardware implementation ability of digital signal processing of undergraduates.","PeriodicalId":164823,"journal":{"name":"2020 International Conference on Artificial Intelligence and Education (ICAIE)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Case Teaching of Parallel FIR Digital Filter Design Combined Matlab with FPGAs\",\"authors\":\"Yi Zheng, Ping Zheng\",\"doi\":\"10.1109/ICAIE50891.2020.00105\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to make undergraduates master a hardware implementation of digital filters, we take the design of a parallel FIR digital low-pass filter as a teaching case, which can present the implementation method of digital filters combining Matlab and a hardware description language together. First, according to the task of the teaching case, the coefficients of FIR digital filter are determined by an FDATool application of Matlab. By normalization and quantization, the filter coefficients and sampled data are both converted from the floating-point data to the fixed-point data. The bit width of valid data bits of FIR filter outputs is determined in accordance with the rule of multiply accumulate operation of FPGAs. Then, we utilize Verilog HDL to implement a fast multiplier and the parallel FIR digital low-pass filter. Finally, we compare the filter outputs of FPGAs with the ones of Matlab, and analyze the reason. The case teaching method, which combines Matlab and FPGAs, is helpful to develop the hardware implementation ability of digital signal processing of undergraduates.\",\"PeriodicalId\":164823,\"journal\":{\"name\":\"2020 International Conference on Artificial Intelligence and Education (ICAIE)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Conference on Artificial Intelligence and Education (ICAIE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAIE50891.2020.00105\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Conference on Artificial Intelligence and Education (ICAIE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAIE50891.2020.00105","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Case Teaching of Parallel FIR Digital Filter Design Combined Matlab with FPGAs
In order to make undergraduates master a hardware implementation of digital filters, we take the design of a parallel FIR digital low-pass filter as a teaching case, which can present the implementation method of digital filters combining Matlab and a hardware description language together. First, according to the task of the teaching case, the coefficients of FIR digital filter are determined by an FDATool application of Matlab. By normalization and quantization, the filter coefficients and sampled data are both converted from the floating-point data to the fixed-point data. The bit width of valid data bits of FIR filter outputs is determined in accordance with the rule of multiply accumulate operation of FPGAs. Then, we utilize Verilog HDL to implement a fast multiplier and the parallel FIR digital low-pass filter. Finally, we compare the filter outputs of FPGAs with the ones of Matlab, and analyze the reason. The case teaching method, which combines Matlab and FPGAs, is helpful to develop the hardware implementation ability of digital signal processing of undergraduates.