带有双极感测放大器的28ns CMOS SRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156709

J. Miyamoto, S. Saitoh, H. Momose, H. Shibata, K. Kanzaki, T. Iizuka

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引用次数: 12

摘要

本报告将讨论一个64K×1 SRAM与双极感测放大器，利用CMOS和双极器件与双聚1.2μm MoSi工艺。SRAM通常在28ns访问，并具有20nA待机模式。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 28ns CMOS SRAM with bipolar sense amplifiers

This report will discuss a 64K×1 SRAM with bipolar sense amplifiers, utilizing both CMOS and bipolar devices with double poly 1.2μm MoSi processing. The SRAM typically accesses in 28ns and has a 20nA standby mode.

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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