T. Brunschwiler, G. Schlottig, A. Sridhar, P. Bezerra, P. Ruch, N. Ebejer, H. Oppermann, J. Kleff, W. Steller, M. Jatlaoui, F. Voiron, Z. Pavlović, P. McCloskey, D. Bremner, P. Parida, F. Krismer, J. Kolar, B. Michel
{"title":"面向立方体大小的计算节点:先进的封装概念实现了极致的3D集成","authors":"T. Brunschwiler, G. Schlottig, A. Sridhar, P. Bezerra, P. Ruch, N. Ebejer, H. Oppermann, J. Kleff, W. Steller, M. Jatlaoui, F. Voiron, Z. Pavlović, P. McCloskey, D. Bremner, P. Parida, F. Krismer, J. Kolar, B. Michel","doi":"10.1109/IEDM.2017.8268322","DOIUrl":null,"url":null,"abstract":"Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Towards cube-sized compute nodes: Advanced packaging concepts enabling extreme 3D integration\",\"authors\":\"T. Brunschwiler, G. Schlottig, A. Sridhar, P. Bezerra, P. Ruch, N. Ebejer, H. Oppermann, J. Kleff, W. Steller, M. Jatlaoui, F. Voiron, Z. Pavlović, P. McCloskey, D. Bremner, P. Parida, F. Krismer, J. Kolar, B. Michel\",\"doi\":\"10.1109/IEDM.2017.8268322\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.\",\"PeriodicalId\":412333,\"journal\":{\"name\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2017.8268322\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268322","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Towards cube-sized compute nodes: Advanced packaging concepts enabling extreme 3D integration
Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.