La2O3/Si堆叠膜的选择性干蚀刻

J. Tonotani
{"title":"La2O3/Si堆叠膜的选择性干蚀刻","authors":"J. Tonotani","doi":"10.1109/IWNC.2006.4570999","DOIUrl":null,"url":null,"abstract":"Summary form given only: A stacked film structure of lanthanum oxide and silicon (La<sub>2</sub>O<sub>3</sub>/Si) is considered to be used in MOSFETs in the Nano-CMOS era since La<sub>2</sub>O<sub>3</sub> is a promising high-k gate insulator. In the substrate contact formation process, La<sub>2</sub>O<sub>3</sub> should be removed selectively against Si substrate. In order to examine the possibility of the selective dry etching of La<sub>2</sub>O<sub>3</sub>/Si stacked film, dry etching characteristics of La<sub>2</sub>O<sub>3</sub> and Si were investigated. As a result, it was found that pure Ar sputtering as well as an addition of Cl<sub>2</sub>, BCl<sub>3</sub> or CF<sub>4</sub> to Ar caused higher etching rate of Si than that of La<sub>2</sub>O<sub>3</sub>, which led to a low etching selectivity. In Ar plasma in a chamber with B contaminations, however, Si was not etched while La<sub>2</sub>O<sub>3</sub> was etched with the etching rate about 2 nm/min. X-ray photoelectron spectroscopy revealed that B existed only on the etched Si surface, which was considered effective for preventing Si from being etched by Ar sputtering. As a conclusion, noble gas plasma, such as Ar plasma, with small amount of B fluxes to the etching surface enables the La<sub>2</sub>O<sub>3</sub>/Si selective etching.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Selective dry etching of La2O3/Si stacked film\",\"authors\":\"J. Tonotani\",\"doi\":\"10.1109/IWNC.2006.4570999\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form given only: A stacked film structure of lanthanum oxide and silicon (La<sub>2</sub>O<sub>3</sub>/Si) is considered to be used in MOSFETs in the Nano-CMOS era since La<sub>2</sub>O<sub>3</sub> is a promising high-k gate insulator. In the substrate contact formation process, La<sub>2</sub>O<sub>3</sub> should be removed selectively against Si substrate. In order to examine the possibility of the selective dry etching of La<sub>2</sub>O<sub>3</sub>/Si stacked film, dry etching characteristics of La<sub>2</sub>O<sub>3</sub> and Si were investigated. As a result, it was found that pure Ar sputtering as well as an addition of Cl<sub>2</sub>, BCl<sub>3</sub> or CF<sub>4</sub> to Ar caused higher etching rate of Si than that of La<sub>2</sub>O<sub>3</sub>, which led to a low etching selectivity. In Ar plasma in a chamber with B contaminations, however, Si was not etched while La<sub>2</sub>O<sub>3</sub> was etched with the etching rate about 2 nm/min. X-ray photoelectron spectroscopy revealed that B existed only on the etched Si surface, which was considered effective for preventing Si from being etched by Ar sputtering. As a conclusion, noble gas plasma, such as Ar plasma, with small amount of B fluxes to the etching surface enables the La<sub>2</sub>O<sub>3</sub>/Si selective etching.\",\"PeriodicalId\":356139,\"journal\":{\"name\":\"2006 International Workshop on Nano CMOS\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Workshop on Nano CMOS\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWNC.2006.4570999\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Workshop on Nano CMOS","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWNC.2006.4570999","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

摘要:由于La2O3是一种很有前途的高k栅极绝缘体,因此在纳米cmos时代mosfet中考虑使用氧化镧和硅(La2O3/Si)的堆叠膜结构。在衬底接触形成过程中,La2O3应选择性地去除Si衬底。为了研究La2O3/Si堆叠膜选择性干刻蚀的可能性,研究了La2O3和Si的干刻蚀特性。结果发现,纯Ar溅射以及在Ar中添加Cl2、BCl3或CF4可以使Si的蚀刻速率高于La2O3,这导致了较低的蚀刻选择性。而在含有B元素的氩气等离子体中,Si未被腐蚀,而La2O3被腐蚀,腐蚀速率约为2 nm/min。x射线光电子能谱显示B只存在于被蚀刻的Si表面,这被认为是防止Si被Ar溅射蚀刻的有效方法。综上所述,稀有气体等离子体,如Ar等离子体,在蚀刻表面具有少量的B通量,可以实现La2O3/Si的选择性蚀刻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Selective dry etching of La2O3/Si stacked film
Summary form given only: A stacked film structure of lanthanum oxide and silicon (La2O3/Si) is considered to be used in MOSFETs in the Nano-CMOS era since La2O3 is a promising high-k gate insulator. In the substrate contact formation process, La2O3 should be removed selectively against Si substrate. In order to examine the possibility of the selective dry etching of La2O3/Si stacked film, dry etching characteristics of La2O3 and Si were investigated. As a result, it was found that pure Ar sputtering as well as an addition of Cl2, BCl3 or CF4 to Ar caused higher etching rate of Si than that of La2O3, which led to a low etching selectivity. In Ar plasma in a chamber with B contaminations, however, Si was not etched while La2O3 was etched with the etching rate about 2 nm/min. X-ray photoelectron spectroscopy revealed that B existed only on the etched Si surface, which was considered effective for preventing Si from being etched by Ar sputtering. As a conclusion, noble gas plasma, such as Ar plasma, with small amount of B fluxes to the etching surface enables the La2O3/Si selective etching.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Selective dry etching of La2O3/Si stacked film Parasitics effects in multi gate MOSFETs Material and interface instabilities of high-κ MOS gate dielectric films Research opportunities for nanoscale CMOS High-resolution TEM/STEM analysis of SiO2/Si(100) and La2O3/Si(100) interfaces
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1