{"title":"一种降低多动态电源电压移电平器功耗的新方法","authors":"M. Terres, C. Meinhardt, G. Bontorin, R. Reis","doi":"10.1109/ICECS.2013.6815514","DOIUrl":null,"url":null,"abstract":"Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically turn off idle LS, using an alternative path to current flows, according to the power mode of the regions that the nets are connected. The main advantages of this technique are when the nets connect regions with the same power mode. In this cases, this technique permits to save more than 35% power consumption and reduce the delay on 30% for NAND2 circuits.","PeriodicalId":117453,"journal":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage\",\"authors\":\"M. Terres, C. Meinhardt, G. Bontorin, R. Reis\",\"doi\":\"10.1109/ICECS.2013.6815514\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically turn off idle LS, using an alternative path to current flows, according to the power mode of the regions that the nets are connected. The main advantages of this technique are when the nets connect regions with the same power mode. In this cases, this technique permits to save more than 35% power consumption and reduce the delay on 30% for NAND2 circuits.\",\"PeriodicalId\":117453,\"journal\":{\"name\":\"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2013.6815514\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2013.6815514","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage
Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically turn off idle LS, using an alternative path to current flows, according to the power mode of the regions that the nets are connected. The main advantages of this technique are when the nets connect regions with the same power mode. In this cases, this technique permits to save more than 35% power consumption and reduce the delay on 30% for NAND2 circuits.