CalmRISC32的缓存系统

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896973

Kilwhan Lee, Jang-Soo Lee, G. Park, Jung-Hoon Lee, T. Han, Shin-Dug Kim, Yongchun Kim, Seh-Woong Jung, Kwang-Yup Lee

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引用次数: 2

摘要

本文介绍了CalmRISC32嵌入式处理器的高速缓存系统。为了提高性能和降低功耗，CalmRISC32采用了一种称为合作缓存的双数据缓存系统结构，该结构利用了双缓存结构的设计灵活性。协作缓存系统应用于数据缓存和指令缓存。本文介绍了CalmRISC32高速缓存系统的结构和工作模型。本文还介绍了CalmRISC32高速缓存系统的实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The cache memory system for CalmRISC32

The cache memory system for CalmRISC32 embedded processor is described in this paper. A dual data cache system structure called a cooperative cache that takes advantage of design flexibilities of a dual cache structure is used as the cache memory system for CalmRISC32 to improve performance and reduce power consumption. The cooperative cache system is applied to both data cache and instruction cache. This paper describes the structure and operational model of the cache memory system for CalmRISC32. The implementation of the cache memory system for CalmRISC32 is also presented.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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