一种新型的6T SRAM单元,具有非对称栅极underlap设计的finfet,可增强读取数据的稳定性和写入能力

S. Salahuddin, Hailong Jiao, V. Kursun
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引用次数: 48

摘要

本文提出了一种基于非对称门搭接工程位线存取晶体管的FinFET存储电路新技术。非对称位线访问晶体管的强度在读操作期间减弱,而在写操作期间由于电流方向相反而增强。与15nm FinFET技术中的标准对称6 -FinFET SRAM单元相比,所提出的非对称6 -FinFET SRAM单元的读取数据稳定性和写入能力分别提高了6.12倍和58%,而不会造成任何面积开销。与具有对称位线访问晶体管的标准6 -FinFET SRAM单元相比,所提出的非对称FinFET SRAM单元的泄漏功耗也降低了高达96.5%。
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A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability
A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors.
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