{"title":"Cmos 0.18 /spl mu/m技术实现的新型超低功耗开关电流有限脉冲响应滤波器","authors":"R. Dlugosz","doi":"10.1109/MIXDES.2006.1706595","DOIUrl":null,"url":null,"abstract":"New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology\",\"authors\":\"R. Dlugosz\",\"doi\":\"10.1109/MIXDES.2006.1706595\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications\",\"PeriodicalId\":318768,\"journal\":{\"name\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2006.1706595\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology
New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications