Cmos 0.18 /spl mu/m技术实现的新型超低功耗开关电流有限脉冲响应滤波器

R. Dlugosz
{"title":"Cmos 0.18 /spl mu/m技术实现的新型超低功耗开关电流有限脉冲响应滤波器","authors":"R. Dlugosz","doi":"10.1109/MIXDES.2006.1706595","DOIUrl":null,"url":null,"abstract":"New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology\",\"authors\":\"R. Dlugosz\",\"doi\":\"10.1109/MIXDES.2006.1706595\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications\",\"PeriodicalId\":318768,\"journal\":{\"name\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2006.1706595\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

本文提出了一种新的开关电流有限脉冲响应滤波器结构。在FIR滤波器中,将存储在延迟线上的信号样本乘以系数,然后求和。对于数字信号和模拟信号,这三种基本操作可以以不同的方式实现。这里提出的SI FIR滤波器结构在电流模式下工作,这意味着输入和输出信号都是电流,所有模拟构建模块都在电流域中工作。样品存储在电流模式采样保持元件中,在电流镜中实现系数乘法,在输出结中实现求和。建议的滤波器不使用运算放大器,因此消耗非常低的功率,这是这里的主要假设。基于所提出的结构,滤波器组可以很容易地实现。本文介绍了一个用CMOS 0.18 mum技术实现的等系数七阶滤波器的实例。该电路的参数非常有前景:芯片面积为5000 μ m²,功耗为150 nW,电源电压为0.5 V。滤波器采用低功耗时钟发生器。所设计的滤波器工作时钟频率高达5 MHz。阻带中的衰减低于40 dB,这对于许多无线传感器网络(WSN)应用来说已经足够了
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New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology
New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications
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