Short channel immunity and current drive capabilities of recessed mosfets in the sub-50 mn regime

IIntroduction Silicon technology is now entering in the sub 0.1 pm range of channel length. In this deep submicron regime, the operating voltage has to be reduced for power dissipation, device reliability and speed performance considerations [ 11. Several scaling analysis have been proposed to explore the ultimate limits of MOSFETs. According to the technological complexity, the outer limit of scaling was found to be 50 and 30 nm in [2] and [3], for epitaxial and dual gate structures, respectively. The control of short channel effects (e.g. threshold voltage roll-off and subthreshold swing increase) severely limits the scaling below 50nm of channel length in conventional planar structures as in [2]. On the other hand, the dual gate structure proposed in [3] exhibits reasonable subthreshold characteristics but still represents a technological challenge and requires gate work function controllability for threshold adjustment. A recessed channel structure is proposed as a technological compromise between dual gate and conventional planar structures. The immunity with respect to short channel effects and the current drive capabilities are extensively studied using drift-diffusion and Monte Carlo simulations.