Length, width and thickness effects in SOI transistors

Without SOI, the future of the microelectronics would be hopeless and the CMOS technology would be useless. SOI does not mean Silicon On Insulator, it comprises any kind of semiconductor, strained or not, on any type of dielectric, with the stringent condition to have ultra-thin layers. This is why the scaling of MOS transistors is intrinsically easier in SOI than in bulk Si, where it is becoming a desperate issue. The nano-size MOS transistor stands as the perfect device for the natural transition from microelectronics to nanoelectronics. In addition, SOI is a most suitable substrate for the implementation of non-classic or pure nanoelectronic components. The dimensions of state-of-the-art SOI MOSFETs are already measurable in nanometers. The aim of this presentation is to illustrate, from an experimental viewpoint, a number of nano-size mechanisms and implications. The scaling beyond 10-nm channel-length is discussed by addressing the main effects: fringing fields, self-heating, transition from partial to full depletion, etc. A good electrostatic control requires nanometer-thick SOI films, where yet another family of mechanisms takes place: super-coupling, volume inversion, and quantization. Finally, the shrinking of the device width enables quantum wire operation and lateral strain or doping effects. A key aspect is that all dimensions need to be reduced concomitantly, not separately. An ultimate SOI MOSFET should be viewed and modelled as a transistor with a miniaturized volume. This is particularly true for innovative devices with multiple gates and/or non-planar configuration. Two, three or four gates can collaborate to bring enhanced performance, functionality, flexibility and scaling. Several device architectures will be evaluated by comparing their merits and ease of processing. Since the device operation is governed by 3-D effects, we will focus on the coupling between the longitudinal, lateral and vertical directions.