用于块级动态电压缩放的片上DC-DC变换器设计要求

2009 Ph.D. Research in Microelectronics and Electronics Pub Date : 2009-07-12 DOI:10.1109/RME.2009.5201374

M. Ichihashi

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引用次数: 1

摘要

本文讨论了块级动态电压缩放(DVS)的片上dc-dc变换器的设计要求。目标应用是低功耗SoC，其中DVS可以应用于所有实现的逻辑块。该变换器仅占用5个键合板，仿真结果表明，在待机模式下，漏电流仅为84 nA。基于一阶模型的一组方程表明，该变换器不需要任何脉冲调频器(PFM)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design requirement of on-chip DC-DC converter for block-level Dynamic Voltage Scaling

This paper discusses the design requirement of on-chip dc-dc converter for block-level Dynamic Voltage Scaling (DVS). The target application is low-power SoC where DVS can be applied to all the implemented logic blocks. The proposed converter occupies only five bonding pads and the simulation demonstrates that the leakage current is only 84 nA in the standby mode. As shown by a set of equations based on a first order model, the proposed converter does not need any pulse frequency modulator (PFM).

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2009 Ph.D. Research in Microelectronics and Electronics

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