{"title":"高性能图形系统中的动态负载平衡","authors":"H. Selzer","doi":"10.2312/EGGH/EGGH91/037-053","DOIUrl":null,"url":null,"abstract":"Interactive 3D graphics applications require significant arithmetic processing to meet the ever-inreasing desire for higher image complexity and higher resolution in displayed images. \n \nThis paper describes a graphics processor architecture with a high degree of parallelism connected to a distributed frame buffer. The architecture can be configured with an arbitrary number of identical, high level programmable processors operating in parallel. \n \nWithin the architecture an automatic load balancing mechanism is presented which distributes the processing load between geometry and rendering section. \n \nAfter the unique features of the architecture are described the load balancing mechanism is analyzed and the increase of performance is demonstrated.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Dynamic Load Balancing within a High Performance Graphics System\",\"authors\":\"H. Selzer\",\"doi\":\"10.2312/EGGH/EGGH91/037-053\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Interactive 3D graphics applications require significant arithmetic processing to meet the ever-inreasing desire for higher image complexity and higher resolution in displayed images. \\n \\nThis paper describes a graphics processor architecture with a high degree of parallelism connected to a distributed frame buffer. The architecture can be configured with an arbitrary number of identical, high level programmable processors operating in parallel. \\n \\nWithin the architecture an automatic load balancing mechanism is presented which distributes the processing load between geometry and rendering section. \\n \\nAfter the unique features of the architecture are described the load balancing mechanism is analyzed and the increase of performance is demonstrated.\",\"PeriodicalId\":206166,\"journal\":{\"name\":\"Advances in Computer Graphics Hardware\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Advances in Computer Graphics Hardware\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.2312/EGGH/EGGH91/037-053\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advances in Computer Graphics Hardware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2312/EGGH/EGGH91/037-053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dynamic Load Balancing within a High Performance Graphics System
Interactive 3D graphics applications require significant arithmetic processing to meet the ever-inreasing desire for higher image complexity and higher resolution in displayed images.
This paper describes a graphics processor architecture with a high degree of parallelism connected to a distributed frame buffer. The architecture can be configured with an arbitrary number of identical, high level programmable processors operating in parallel.
Within the architecture an automatic load balancing mechanism is presented which distributes the processing load between geometry and rendering section.
After the unique features of the architecture are described the load balancing mechanism is analyzed and the increase of performance is demonstrated.