NMOS digital integrated circuits in 6h silicon carbide

N-channel MOSFETs are fabricatedin p-type epilayers grown on a p+ (Si-face) 6H-Sic substrate. The epilayers are doped with A1 to 2x1016 cm-3, and are 3 pm thick. Substrates with epilayers were obtained from Cree Research, Durham, NC. Registration marks are produced by R E using an aluminum etch mask. Source and drain regions are then formed by selective-area ion implantation of N to a concentration of lx1019 cm-3. A second implant introduces A1 at a concentration of 1x1018 cm-3 into regions outside the active devices to serve as a chanstop. Both implantations are masked with Ti and are conducted with the sample at an elevated temperature. The implants are then activated at the same time by a high temperature anneal in Ar. A 500 8, thick gate oxide is grown by wet thermal oxidation at 1150 OC, followed by a 30 min. in-situ anneal in Ar. Source and drain ohmic contacts are formed by E-beam evaporated Ni, which is pattemed by liftoff. p-type ohmic contacts are also formed to the chanstop region by evaporation of Al, which is also pattemed by liftoff. Both ohmic contacts are then annealed at high temperature in Ar. Finally, gate and interconnect metal is formed by evaporated AI, forming non-selfaligned metal-gate MOSFETs.