8层3D垂直Ru/AlOxNy/TiN RRAM与Mega-Ω级LRS低功耗和超高密度存储器

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830164

S. Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Wong, H. P. Wong

{"title":"8层3D垂直Ru/AlOxNy/TiN RRAM与Mega-Ω级LRS低功耗和超高密度存储器","authors":"S. Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Wong, H. P. Wong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830164","DOIUrl":null,"url":null,"abstract":"We present an 8-layer 3D vertical Ru/AlOxNy/TiN RRAM device integrated with a transistor as current driver at the end of the vertical pillar. This RRAM cell is designed for low power and ultrahigh-density non-volatile memory: 1) a large low-resistance state (LRS) value of around 1 MΩ with an ON/OFF window of > 102 to ensure successful write/read operations for the worst-case cell in the array; 2) a thin (15 nm) Ru word-plane (WP) electrode to reduce parasitic resistance yet scalable vertically to > 128 layers; 3) 2-bit-per-cell capability that doubles the memory capacity. A 128-layer 3D vertical RRAM with Ru/AlOxNy/TiN can achieve bit density of 29.5 Gb/mm2 with 2 bits per cell and CMOS under Array (CuA), based on simulations that include leakage current, pillar, and WP resistances. Reliability tests show the RRAM cell can be reliably switched up to 3×106 write/read cycles and maintain stable resistance states > 104 s at 85 °C.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory\",\"authors\":\"S. Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Wong, H. P. Wong\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830164\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present an 8-layer 3D vertical Ru/AlOxNy/TiN RRAM device integrated with a transistor as current driver at the end of the vertical pillar. This RRAM cell is designed for low power and ultrahigh-density non-volatile memory: 1) a large low-resistance state (LRS) value of around 1 MΩ with an ON/OFF window of > 102 to ensure successful write/read operations for the worst-case cell in the array; 2) a thin (15 nm) Ru word-plane (WP) electrode to reduce parasitic resistance yet scalable vertically to > 128 layers; 3) 2-bit-per-cell capability that doubles the memory capacity. A 128-layer 3D vertical RRAM with Ru/AlOxNy/TiN can achieve bit density of 29.5 Gb/mm2 with 2 bits per cell and CMOS under Array (CuA), based on simulations that include leakage current, pillar, and WP resistances. Reliability tests show the RRAM cell can be reliably switched up to 3×106 write/read cycles and maintain stable resistance states > 104 s at 85 °C.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830164\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

我们提出了一个8层3D垂直Ru/AlOxNy/TiN RRAM器件，在垂直柱的末端集成了一个晶体管作为电流驱动器。该RRAM单元设计用于低功耗和超高密度非易失性存储器:1)具有约1 MΩ的大低阻状态(LRS)值和> 102的ON/OFF窗口，以确保阵列中最坏情况单元的成功写/读操作;2)一个薄的(15 nm) Ru字平面(WP)电极，可以降低寄生电阻，但垂直可扩展到> 128层;3)每单元2位的能力，使内存容量加倍。基于泄漏电流、柱电阻和WP电阻的模拟，采用Ru/AlOxNy/TiN的128层3D垂直RRAM可以实现29.5 Gb/mm2的位密度，每个单元2位，CMOS在阵列(CuA)下。可靠性测试表明，RRAM单元可以可靠地切换到3×106写/读周期，并在85°C下保持> 104 s的稳定电阻状态。

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8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory

We present an 8-layer 3D vertical Ru/AlOxNy/TiN RRAM device integrated with a transistor as current driver at the end of the vertical pillar. This RRAM cell is designed for low power and ultrahigh-density non-volatile memory: 1) a large low-resistance state (LRS) value of around 1 MΩ with an ON/OFF window of > 102 to ensure successful write/read operations for the worst-case cell in the array; 2) a thin (15 nm) Ru word-plane (WP) electrode to reduce parasitic resistance yet scalable vertically to > 128 layers; 3) 2-bit-per-cell capability that doubles the memory capacity. A 128-layer 3D vertical RRAM with Ru/AlOxNy/TiN can achieve bit density of 29.5 Gb/mm2 with 2 bits per cell and CMOS under Array (CuA), based on simulations that include leakage current, pillar, and WP resistances. Reliability tests show the RRAM cell can be reliably switched up to 3×106 write/read cycles and maintain stable resistance states > 104 s at 85 °C.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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