{"title":"用于SoC应用的流水线Flash ADC的设计、综合和性能测量","authors":"Mingzhen Wang, C. Chen","doi":"10.1109/IMTC.2005.1604060","DOIUrl":null,"url":null,"abstract":"This paper presents a design synthesis and performance measurement of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC in 130 nanometer CMOS. CMOS technology has superior performance of sampling rate of 2.5 GHz for input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC","PeriodicalId":244878,"journal":{"name":"2005 IEEE Instrumentationand Measurement Technology Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Design Synthesis and Performance Measurement of Pipelined Flash ADC for SoC Applications\",\"authors\":\"Mingzhen Wang, C. Chen\",\"doi\":\"10.1109/IMTC.2005.1604060\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a design synthesis and performance measurement of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC in 130 nanometer CMOS. CMOS technology has superior performance of sampling rate of 2.5 GHz for input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC\",\"PeriodicalId\":244878,\"journal\":{\"name\":\"2005 IEEE Instrumentationand Measurement Technology Conference Proceedings\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE Instrumentationand Measurement Technology Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMTC.2005.1604060\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Instrumentationand Measurement Technology Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.2005.1604060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design Synthesis and Performance Measurement of Pipelined Flash ADC for SoC Applications
This paper presents a design synthesis and performance measurement of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC in 130 nanometer CMOS. CMOS technology has superior performance of sampling rate of 2.5 GHz for input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC
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