A compact adderless feed-forward incremental \(\varDelta \varSigma \) with multiple global references for CMOS image sensors

This paper presents an adderless feed-forward incremental \(\varDelta \varSigma \) (I\(\varDelta \varSigma \)) with asynchronous SAR (ASAR) that removes the need for in-column calibration by using global references, eliminates an additional summing amplifier and reduces the conversion time by using a multi-bit ASAR quantizer. The proposed I\(\varDelta \varSigma \) ADC is designed in 40 nm CMOS technology and is laid out compactly in a 5 \(\upmu \)m × 466 \(\upmu \)m column. According to post-layout simulations, the ADC achieves an input-referred noise of 85 \(\upmu \)V\(_{ rms }\), a conversion time of 3.2 \(\upmu \)s (with DCDS) and a power consumption of 230 \(\upmu \)W. This results in a Walden FoM\(_{\textrm{W}}\) of 234 fJ/conv.step and a FoM\(_{\textrm{A}}\) = FoM\(_{\textrm{W}} \times \text {A}_{\text {ADC}}\) of 0.54 fJ\(\cdot \)mm\(^2\)/conv.step, which demonstrates the feasibility of using the proposed architecture in CMOS image sensors.