{"title":"一种采用40纳米CMOS的130 ghz低面积功率放大器","authors":"Jaegwan Kim, Changjung Lee, Munkyo Seo","doi":"10.5515/kjkiees.2023.34.4.310","DOIUrl":null,"url":null,"abstract":"This paper presents a 130 GHz differential common-source architecture power amplifier using a 40-nm CMOS process. To ensure proper matching between the stages, except for the output, a transformer was used to achieve conjugate matching. For the output, a balun was used to match it to the maximum output load impedance. On-wafer tests showed that the maximum gain of the amplifier was 22.5 dB at 130 GHz, the 3-dB bandwidth was 15 GHz, and the output saturation power was 7.7 dBm. At a supply voltage of 1 V, the power consumption was 81 mW, and PAE was 7.1 % at a saturated output power. The chip area, excluding the pads, was 388 μm×168 μm.","PeriodicalId":55817,"journal":{"name":"Journal of the Korean Institute of Electromagnetic Engineering and Science","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 130-GHz Low-Area Power Amplifier in 40-nm CMOS\",\"authors\":\"Jaegwan Kim, Changjung Lee, Munkyo Seo\",\"doi\":\"10.5515/kjkiees.2023.34.4.310\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 130 GHz differential common-source architecture power amplifier using a 40-nm CMOS process. To ensure proper matching between the stages, except for the output, a transformer was used to achieve conjugate matching. For the output, a balun was used to match it to the maximum output load impedance. On-wafer tests showed that the maximum gain of the amplifier was 22.5 dB at 130 GHz, the 3-dB bandwidth was 15 GHz, and the output saturation power was 7.7 dBm. At a supply voltage of 1 V, the power consumption was 81 mW, and PAE was 7.1 % at a saturated output power. The chip area, excluding the pads, was 388 μm×168 μm.\",\"PeriodicalId\":55817,\"journal\":{\"name\":\"Journal of the Korean Institute of Electromagnetic Engineering and Science\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of the Korean Institute of Electromagnetic Engineering and Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5515/kjkiees.2023.34.4.310\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of the Korean Institute of Electromagnetic Engineering and Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5515/kjkiees.2023.34.4.310","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a 130 GHz differential common-source architecture power amplifier using a 40-nm CMOS process. To ensure proper matching between the stages, except for the output, a transformer was used to achieve conjugate matching. For the output, a balun was used to match it to the maximum output load impedance. On-wafer tests showed that the maximum gain of the amplifier was 22.5 dB at 130 GHz, the 3-dB bandwidth was 15 GHz, and the output saturation power was 7.7 dBm. At a supply voltage of 1 V, the power consumption was 81 mW, and PAE was 7.1 % at a saturated output power. The chip area, excluding the pads, was 388 μm×168 μm.
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