TeRa: Ternary and Range based packet classification engine

This work proposes a novel approach to the hardware implementation of packet classification in ASICs, using NAND-NOR logic at each stage. The proposed design utilizes modified ternary encoding to process the prefix field, resulting in a two-level NAND-NOR logic for prefix processing. The field representation based on classbench rules helps reduce memory usage by almost 45% compared to conventional prefix representations. Additionally, an efficient range matching solution is implemented using a carry tree logic that relies on 1’s and 2’s Complement subtraction. The integration of a carry-based range comparator enhances hardware optimization for range processing without the need for prefix conversion. Additionally, match inversion logic streamlines the processing of exceptional or inverse fields without incurring extra hardware overhead. This work also presents a specialized logic circuit for ternary and range matching, complemented by a specialized priority grouping technique. The proposed architecture, including TYPE1 and TYPE2, achieves throughput rates of 9.9 BPPS and 6.6 BPPS, respectively, while supporting both best-match and multi-match addresses within the same hardware environment.