Peng Wang;Rishika Agarwala;Natalie B. Ownby;Xinjian Liu;Benton H. Calhoun
{"title":"用于心率、血氧饱和度和脉搏传输时间协同监测的 2.3-5.7μW 三模式自适应光敏传感器接口集成电路。","authors":"Peng Wang;Rishika Agarwala;Natalie B. Ownby;Xinjian Liu;Benton H. Calhoun","doi":"10.1109/TBCAS.2024.3360140","DOIUrl":null,"url":null,"abstract":"This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO\n<sub>2</sub>\n, and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84 \n<italic>μ</i>\nA maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3–5.7 \n<italic>μ</i>\nW AFE power and 1.52 mm\n<sup>2</sup>\n die area with 102dB (SpO\n<sub>2</sub>\n mode), 110–116 dB (HR & PTT mode) dynamic range. A SpO\n<sub>2</sub>\n test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9 \n<italic>μ</i>\nW and 43.7 \n<italic>μ</i>\nW system power, respectively.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 2.3–5.7 μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2, and Pulse Transit Time Co-Monitoring\",\"authors\":\"Peng Wang;Rishika Agarwala;Natalie B. Ownby;Xinjian Liu;Benton H. Calhoun\",\"doi\":\"10.1109/TBCAS.2024.3360140\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO\\n<sub>2</sub>\\n, and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84 \\n<italic>μ</i>\\nA maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3–5.7 \\n<italic>μ</i>\\nW AFE power and 1.52 mm\\n<sup>2</sup>\\n die area with 102dB (SpO\\n<sub>2</sub>\\n mode), 110–116 dB (HR & PTT mode) dynamic range. A SpO\\n<sub>2</sub>\\n test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9 \\n<italic>μ</i>\\nW and 43.7 \\n<italic>μ</i>\\nW system power, respectively.\",\"PeriodicalId\":94031,\"journal\":{\"name\":\"IEEE transactions on biomedical circuits and systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-01-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE transactions on biomedical circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10416712/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE transactions on biomedical circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10416712/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.3–5.7 μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2, and Pulse Transit Time Co-Monitoring
This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO
2
, and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84
μ
A maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3–5.7
μ
W AFE power and 1.52 mm
2
die area with 102dB (SpO
2
mode), 110–116 dB (HR & PTT mode) dynamic range. A SpO
2
test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9
μ
W and 43.7
μ
W system power, respectively.