Sola Woo;Khandker Akif Aabrar;Suman Datta;Shimeng Yu
{"title":"分析铁电 FinFET 中总电离剂量诱导的内存窗口退化","authors":"Sola Woo;Khandker Akif Aabrar;Suman Datta;Shimeng Yu","doi":"10.1109/TDMR.2023.3344710","DOIUrl":null,"url":null,"abstract":"The total-ionizing-dose (TID) effect of ferroelectric FinFET structure (Fe-FinFET) is analyzed under various gamma ray irradiation conditions. An TCAD model is developed to understand the physical mechanism of TID effect, and the simulation results are calibrated with the experimental data. We show that the TID-induced memory window degradation is attributed to two types of traps being generated within the ferroelectric layer and at the interfacial layer/silicon interface. Furthermore, the impact of the scaling down the Fe-FinFET structure is investigated with various gate lengths and fin widths. The projection shows that the scaled Fe-FinFET still could maintain a 0.4 V memory window under the highest radiation dose (10 Mrad). The sufficient memory window under the highest irradiation condition confirms the survivability of the Fe-FinFETs and makes Fe-FinFET a promising candidate for data storage as radiation-hard non-volatile memory in harsh ionizing environment.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"84-88"},"PeriodicalIF":2.5000,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analyzing Total-Ionizing-Dose Induced Memory Window Degradation in Ferroelectric FinFET\",\"authors\":\"Sola Woo;Khandker Akif Aabrar;Suman Datta;Shimeng Yu\",\"doi\":\"10.1109/TDMR.2023.3344710\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The total-ionizing-dose (TID) effect of ferroelectric FinFET structure (Fe-FinFET) is analyzed under various gamma ray irradiation conditions. An TCAD model is developed to understand the physical mechanism of TID effect, and the simulation results are calibrated with the experimental data. We show that the TID-induced memory window degradation is attributed to two types of traps being generated within the ferroelectric layer and at the interfacial layer/silicon interface. Furthermore, the impact of the scaling down the Fe-FinFET structure is investigated with various gate lengths and fin widths. The projection shows that the scaled Fe-FinFET still could maintain a 0.4 V memory window under the highest radiation dose (10 Mrad). The sufficient memory window under the highest irradiation condition confirms the survivability of the Fe-FinFETs and makes Fe-FinFET a promising candidate for data storage as radiation-hard non-volatile memory in harsh ionizing environment.\",\"PeriodicalId\":448,\"journal\":{\"name\":\"IEEE Transactions on Device and Materials Reliability\",\"volume\":\"24 1\",\"pages\":\"84-88\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2023-12-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Device and Materials Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10366869/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10366869/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
摘要
分析了铁电 FinFET 结构（Fe-FinFET）在各种伽马射线辐照条件下的总电离剂量（TID）效应。为了理解 TID 效应的物理机制，我们建立了一个 TCAD 模型，并将模拟结果与实验数据进行了校准。结果表明，TID 引起的存储器窗口劣化可归因于铁电层内和界面层/硅界面上产生的两种陷阱。此外，我们还利用不同的栅极长度和鳍片宽度研究了缩小 Fe-FinFET 结构的影响。预测结果表明，在最高辐射剂量（10 Mrad）下，按比例缩小的 Fe-FinFET 仍能保持 0.4 V 的存储窗口。在最高辐照条件下仍能保持足够的存储窗口证实了 Fe-FinFET 的存活能力，并使 Fe-FinFET 成为在严酷电离环境中作为抗辐射非易失性存储器进行数据存储的理想候选器件。
Analyzing Total-Ionizing-Dose Induced Memory Window Degradation in Ferroelectric FinFET
The total-ionizing-dose (TID) effect of ferroelectric FinFET structure (Fe-FinFET) is analyzed under various gamma ray irradiation conditions. An TCAD model is developed to understand the physical mechanism of TID effect, and the simulation results are calibrated with the experimental data. We show that the TID-induced memory window degradation is attributed to two types of traps being generated within the ferroelectric layer and at the interfacial layer/silicon interface. Furthermore, the impact of the scaling down the Fe-FinFET structure is investigated with various gate lengths and fin widths. The projection shows that the scaled Fe-FinFET still could maintain a 0.4 V memory window under the highest radiation dose (10 Mrad). The sufficient memory window under the highest irradiation condition confirms the survivability of the Fe-FinFETs and makes Fe-FinFET a promising candidate for data storage as radiation-hard non-volatile memory in harsh ionizing environment.
期刊介绍：
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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