{"title":"最佳匹配 189-232 GHz 6.8 dBm 输出功率 CMOS 倍频器","authors":"Ruibing Dong, Shinsuke Hara, Mohamed H. Mubarak, Satoru Tanoi, Tatsuo Hagino, Issei Watanabe, Akifumi Kasamatsu","doi":"10.1155/2024/9979639","DOIUrl":null,"url":null,"abstract":"<div>\n <p>This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm<sup>2</sup> and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.</p>\n </div>","PeriodicalId":54944,"journal":{"name":"International Journal of RF and Microwave Computer-Aided Engineering","volume":null,"pages":null},"PeriodicalIF":0.9000,"publicationDate":"2024-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1155/2024/9979639","citationCount":"0","resultStr":"{\"title\":\"Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler\",\"authors\":\"Ruibing Dong, Shinsuke Hara, Mohamed H. Mubarak, Satoru Tanoi, Tatsuo Hagino, Issei Watanabe, Akifumi Kasamatsu\",\"doi\":\"10.1155/2024/9979639\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div>\\n <p>This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm<sup>2</sup> and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.</p>\\n </div>\",\"PeriodicalId\":54944,\"journal\":{\"name\":\"International Journal of RF and Microwave Computer-Aided Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.9000,\"publicationDate\":\"2024-03-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://onlinelibrary.wiley.com/doi/epdf/10.1155/2024/9979639\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of RF and Microwave Computer-Aided Engineering\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1155/2024/9979639\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of RF and Microwave Computer-Aided Engineering","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1155/2024/9979639","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS","Score":null,"Total":0}
Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler
This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795 mm2 and shows a total DC power dissipation of 262 mW and DC-RF efficiency of 1.87%.
期刊介绍:
International Journal of RF and Microwave Computer-Aided Engineering provides a common forum for the dissemination of research and development results in the areas of computer-aided design and engineering of RF, microwave, and millimeter-wave components, circuits, subsystems, and antennas. The journal is intended to be a single source of valuable information for all engineers and technicians, RF/microwave/mm-wave CAD tool vendors, researchers in industry, government and academia, professors and students, and systems engineers involved in RF/microwave/mm-wave technology.
Multidisciplinary in scope, the journal publishes peer-reviewed articles and short papers on topics that include, but are not limited to. . .
-Computer-Aided Modeling
-Computer-Aided Analysis
-Computer-Aided Optimization
-Software and Manufacturing Techniques
-Computer-Aided Measurements
-Measurements Interfaced with CAD Systems
In addition, the scope of the journal includes features such as software reviews, RF/microwave/mm-wave CAD related news, including brief reviews of CAD papers published elsewhere and a "Letters to the Editor" section.