Local deadlock analysis of Simulink models based on timed behavioural patterns and theorem proving

Compositional deadlock analysis of process networks is a well-known challenge. We propose a compositional deadlock analysis strategy for timed process networks, more specifically, those obtained from Simulink multi-rate block diagrams. We handle models with both acyclic and cyclic communication graphs. Particularly, the latter naturally happens in Simulink models with feedback, among other kinds of cycles. Since there is no general solution to analyse cyclic models in a compositional way, we explore the use of behavioural patterns that allow the verification to be carried out in a compositional fashion. We represent process networks in tock-CSP, a dialect of CSP that allows modelling time aspects using a special tock event. The verification approach is implemented as a new package in CSP-Prover, a theorem prover for CSP which is itself implemented in Isabelle/HOL. To illustrate the overall approach and, particularly, how it can scale, we consider several variations of an actuation system with increasing complexity. We show that the examples are instances of the client/server and the asynchronous dynamic timed behaviour patterns. These patterns and all verification steps are formalised using CSP-Prover.