探索在垂直纳米线中堆叠器件以实现 CMOS 逆变器的适用性

IF 2.1 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Nanotechnology Pub Date : 2024-03-23 DOI:10.1109/TNANO.2024.3404615

E. Amat;A. del Moral;J. Bausells;F. Perez-Murano

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引用次数: 0

摘要

利用垂直拓扑结构在三维配置中堆叠器件被认为是提高电子器件和电路性能的下一步。例如，可以通过连续沉积金属间层和金属层来制造 CMOS 反相器。我们使用 Sentaurus 3D TCAD 软件模拟了这种新的集成电路制造方案。我们分析了不同器件设计参数的影响，以优化其性能。最后，我们还探讨了利用所提出的叠层实现 5 级环形振荡器电路的可行性。

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Exploring the Suitability of Stacking Devices in a Vertical Nanowire to Implement a CMOS Inverter

Stacking devices in a 3D configuration by using a vertical topology is considered as the next step to improve electronic devices and circuits performance. For instance, a CMOS inverted can be built by continuously depositing both inter-metal and metal layers. This new IC manufacturing proposal has been simulated by using Sentaurus 3D TCAD software. We have analyzed the influence of different device design parameters to optimize its performance. Finally, we have also explored the feasibility to implement a 5-stage ring oscillator circuit by using the proposed stack.

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来源期刊

IEEE Transactions on Nanotechnology 工程技术-材料科学：综合

CiteScore

4.80

自引率

8.30%

发文量

审稿时长

8.3 months

期刊介绍： The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.