Study of the high-k/SiO2 stacked gate micro-pattern trench CSTBT

To alleviate the challenge of threshold voltage (V_TH) variations in carrier stored trench-gate bipolar transistor (CSTBT) induced by the CS layer and to prevent erroneous turn-on of CSTBT at elevated temperatures, we propose a high-k/SiO₂ stacked gate dielectric layer structure for CSTBT, termed HKO-CSTBT. Due to the effect of the high-k material reducing the V_TH, HKO-CSTBT enables the adoption of a higher P-body doping concentration. While keeping the V_TH unchanged, HKO-CSTBT increase the doping concentration difference between the CS layer and the P-body, and diminishes the influence of the CS layer on the channel region. This leads to a more uniform V_TH across different cells or devices under specific ion implantation errors, reducing V_TH deviation by over 65 %. This consistency is advantageous for the parallel configuration of devices. Employing a high-k material as the dielectric layer also decreases the absolute value of the device's V_TH temperature coefficient. At a temperature of 450 K, the V_TH of the HKO-CSTBT is 0.237 V higher than its conventional counterpart, favoring its operation under elevated temperature. Furthermore, at elevated temperatures, when a high voltage is applied to the collector-emitter, the excellent dielectric properties of the high-k material results in a reduced electric field peak at the bottom of the gate. The HKO-CSTBT also allows a higher CS layer ion implantation dose, subsequently decreasing the on-state saturation voltage (V_CE(sat)). In short, unlike the previous high-k materials used in power devices only to improve the super-junction technology, this paper presents a new application and function of high-k materials in power devices.