{"title":"利用单元交互方法设计基于 QCA 的通用可逆逻辑门架构并优化其功耗","authors":"Aamir Suhail Taray , Satyendra Kumar Singh , Yogesh Singh , Farah Naaz , Purnima Hazra","doi":"10.1016/j.microrel.2024.115446","DOIUrl":null,"url":null,"abstract":"<div><p>This paper introduces a new design for 3 <strong>×</strong> 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm<sup>2</sup> and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm<sup>2</sup> and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115446"},"PeriodicalIF":1.6000,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach\",\"authors\":\"Aamir Suhail Taray , Satyendra Kumar Singh , Yogesh Singh , Farah Naaz , Purnima Hazra\",\"doi\":\"10.1016/j.microrel.2024.115446\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper introduces a new design for 3 <strong>×</strong> 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm<sup>2</sup> and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm<sup>2</sup> and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.</p></div>\",\"PeriodicalId\":51131,\"journal\":{\"name\":\"Microelectronics Reliability\",\"volume\":\"159 \",\"pages\":\"Article 115446\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2024-06-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0026271424001264\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424001264","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach
This paper introduces a new design for 3 × 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm2 and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm2 and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.
期刊介绍:
Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged.
Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.