利用单元交互方法设计基于 QCA 的通用可逆逻辑门架构并优化其功耗

IF 1.6 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Reliability Pub Date : 2024-06-20 DOI:10.1016/j.microrel.2024.115446
Aamir Suhail Taray , Satyendra Kumar Singh , Yogesh Singh , Farah Naaz , Purnima Hazra
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引用次数: 0

摘要

本文介绍了一种新的 3 × 3 通用可逆逻辑门设计,即 RLG-QCA(可逆逻辑门-量子点蜂窝自动机),它是利用 QCA 技术实现的。我们设计的基本概念基于多数投票门方法(MVA)。我们采用精确的 QCA 单元交互方法对建议的门进行了设计、模拟和优化。建议的栅极没有交叉。它的总面积为 0.0311 μm2,延迟时间仅为 0.5 个时间周期。为了验证其通用性,我们使用所提出的 RLG-QCA 逻辑门实现了所有七个一级逻辑门和十三种布尔算法。然后,仅用两个拟议的通用逻辑门和一个共面单元分频器就构建了一个一位全加法器电路。所提出的架构似乎是一种超高效且稳定的架构,总单元数为 53 个,总单元面积仅为 0.0175 μm2。最后,还对所提出的 RLG-QCA 栅极以及全加法器电路在不同能级下进行了能量耗散分析,以确认所提出的栅极在超低功耗设计应用中的可持续性和适用性。结果表明,该设计的能耗极低,这也是该设计在实现低功耗数字电路方面的一大优势。
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Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach

This paper introduces a new design for 3 × 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm2 and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm2 and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.

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来源期刊
Microelectronics Reliability
Microelectronics Reliability 工程技术-工程:电子与电气
CiteScore
3.30
自引率
12.50%
发文量
342
审稿时长
68 days
期刊介绍: Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.
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