A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test

—The built-in self-test (BIST) circuit is designed to be highly integrated with ADC under test and tests the static linearity based on the stimulus error identification and removal (SEIR) method. A novel level shift generator is proposed for high-precision ADC testing to break the resolution limitation caused by thermal noise and non-linearity. The double sampling operation realized by the chopper circuits cancels the sampling kT/C noise, and the circuit further reduces the amplifier's thermal noise by reducing the noise bandwidth. Besides, this paper presents a new method to achieve a highly linearity-constant voltage shift by applying the negative-C technique. Implemented in 180 nm CMOS process, the simulation results show that the noise power of the voltage shift is reduced by 10 dB, and the constancy of voltage shift is only 3.7 ppm over the entire ADC input range. Benefitting from the noise and linearity performance enhancement, this BIST circuit can test 18-bit ADC to 18-bit accuracy level with one-tenth sampling points.