An ultra-low power fully CMOS sub-bandgap reference in weak inversion

This paper presents a sub-1-V CMOS bandgap reference circuit with ultra-low power consumption, utilizing only 9 MOS transistors. The proposed circuit achieves nano-watt power consumption by biasing all transistors in the sub-threshold region. A three-branched configuration is utilized to create the bandgap voltage reference in the circuit. The proposed architecture generates CTAT and PTAT voltages without using any op-amp and BJT. In this circuit, the cascode structure are used to improve the line sensitivity (LS). In the proposed bandgap circuit, self-biased configuration is used without using an external bias circuitry. The first branch generates PTAT current and the second and third branches generate PTAT and CTAT voltages. The bandgap circuit is designed and simulated using Cadence in TSMC 0.18 μm CMOS technology. The results of post-layout simulation indicate that the bandgap voltage reference circuit generates a voltage reference of 644 mV, with a temperature coefficient (TC) of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The proposed circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. Furthermore, the circuit exhibits a line sensitivity of 0.31%/V for power supply voltages ranging from 0.9 to 1.8 V. The Power Supply Ripple Rejection (PSRR) of the proposed circuit is about − 40 dB within the frequency range of 1–100 Hz.