The effect of switching and cycle-to-cycle variations of RRAM on 4-bit encryption/decryption process

The resistive RAM (RRAM) based in-memory computation is a promising technology to overcome the Von-Neumann bottleneck to provide fast and efficient computation. The RRAM is the most appropriate choice for cryptographic applications like encryption/decryption in which the data is computed and stored in the memory itself which enhances the security. The variability issue of RRAM namely switching or device parameter variations and cycle-to-cycle variations deteriorates the functionality of RRAM based circuits. In this paper, the XOR gate with V/R-R logic and a 4-bit encryption/decryption process are implemented using the RRAM Stanford model integrated in the Cadence circuit simulator. The output voltage variations of XOR gate and the encryption/decryption by varying switching and cycle-to-cycle parameters are analyzed. The range of switching parameters of the model that provides the accurate outputs of XOR gate and encryption/decryption is determined.