Novel accurate steady-state thermal resistance model for power chips embedded in TTSVs heat dissipation array

a novel oblique pyramid equivalent heat dissipation model is proposed for theoretically analyzing heat dissipation capacity of power chips with embedded TTSVs. Extra carefully researching correction of oblique thermal resistance, additional lateral thermal resistance, and thermal resistance of TSV insulation sleeve, the accurate theoretical thermal resistance model was established. Setting the FEA simulating results based on COMSOL Multiphysics as benchmark, heat dissipation effects of variation of radius of TTSV (r), thickness of the power chip (H₀), and side length of the single cell (L₀) have been numerically investigated. The maximum temperature relative error of the proposed model with FEA simulated results is not more than 0.2 %, 1 %, and 0.5 % for variation of r, H₀, and L₀, respectively. The proposed model has been theoretically and numerically proven to be effective and accurate.