A high-light-load-efficiency hysteresis-controlled buck converter with adaptively clocked hysteresis dynamic comparator for IoT applications

A hysteresis-controlled (HC) buck converter with an adaptively clocked hysteresis dynamic comparator (ACHDC) is proposed to improve the conversion efficiency at light load. In contrast to the conventional HC buck converter, a comparator with enabled signal is applied to replace the continuously-on comparator, resulting in significantly reduced static power consumption from the comparator. Additionally, the converter employs an adaptive clock scaling circuit (ACSC) for the dynamic comparator, enabling it to achieve high conversion efficiency across a load current range of 1 μA to 20 mA, with minimal deterioration in ripple voltage. To generate the clock signal, a leakage-based oscillator with dual regulation of capacitance and current is designed. Simulation results demonstrate that the proposed buck converter achieves a peak efficiency of 94.83 % and maintains an efficiency of at least 86.47 % over the entire load range.