{"title":"非共面铜柱存在时压力对芯片堆栈结构稳定性的影响","authors":"Yu Li;Li Liu;Meng Ruan;Zhengzhi Wang;Sheng Liu;Zhiwen Chen","doi":"10.1109/TCPMT.2024.3416108","DOIUrl":null,"url":null,"abstract":"Cu-Cu bonding is widely used in 3-D stacking for chip interconnection. However, noncoplanarity of Cu pillars can significantly influence the reliability of the stacked chips. In this work, the impacts of bonding pressures on chip stacking with noncoplanar Cu pillars were investigated through finite element modeling and molecular dynamics (MDs) simulations. From finite element modeling, the maximum residual stress in the TSV was located in the bottom Cu pillar furthest from the center of the chip and increased with bonding pressure. It was also found that the overall warpage increased linearly with the number of chip layers initially and then stabilized when Cu pillars were noncoplanar. The linear increase rate raised with higher bonding pressure. Based on MDs simulations, the thickness of bonding layer in the shorter pillar increased continuously with bonding time and pressure. In contrast, the thickness in standard pillars grew over time and eventually stabilized. During this, the bonding pressure posed negligible effects on the bonding layer thickness in standard pillars, and dislocations were generally concentrated near the bonding layer, serving as channels for Cu atom diffusion into the bonding layer.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 7","pages":"1207-1214"},"PeriodicalIF":2.3000,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impacts of Pressure on the Stability of Chip Stack Structures in the Presence of Noncoplanar Cu Pillars\",\"authors\":\"Yu Li;Li Liu;Meng Ruan;Zhengzhi Wang;Sheng Liu;Zhiwen Chen\",\"doi\":\"10.1109/TCPMT.2024.3416108\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cu-Cu bonding is widely used in 3-D stacking for chip interconnection. However, noncoplanarity of Cu pillars can significantly influence the reliability of the stacked chips. In this work, the impacts of bonding pressures on chip stacking with noncoplanar Cu pillars were investigated through finite element modeling and molecular dynamics (MDs) simulations. From finite element modeling, the maximum residual stress in the TSV was located in the bottom Cu pillar furthest from the center of the chip and increased with bonding pressure. It was also found that the overall warpage increased linearly with the number of chip layers initially and then stabilized when Cu pillars were noncoplanar. The linear increase rate raised with higher bonding pressure. Based on MDs simulations, the thickness of bonding layer in the shorter pillar increased continuously with bonding time and pressure. In contrast, the thickness in standard pillars grew over time and eventually stabilized. During this, the bonding pressure posed negligible effects on the bonding layer thickness in standard pillars, and dislocations were generally concentrated near the bonding layer, serving as channels for Cu atom diffusion into the bonding layer.\",\"PeriodicalId\":13085,\"journal\":{\"name\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"volume\":\"14 7\",\"pages\":\"1207-1214\"},\"PeriodicalIF\":2.3000,\"publicationDate\":\"2024-06-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10560036/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10560036/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Impacts of Pressure on the Stability of Chip Stack Structures in the Presence of Noncoplanar Cu Pillars
Cu-Cu bonding is widely used in 3-D stacking for chip interconnection. However, noncoplanarity of Cu pillars can significantly influence the reliability of the stacked chips. In this work, the impacts of bonding pressures on chip stacking with noncoplanar Cu pillars were investigated through finite element modeling and molecular dynamics (MDs) simulations. From finite element modeling, the maximum residual stress in the TSV was located in the bottom Cu pillar furthest from the center of the chip and increased with bonding pressure. It was also found that the overall warpage increased linearly with the number of chip layers initially and then stabilized when Cu pillars were noncoplanar. The linear increase rate raised with higher bonding pressure. Based on MDs simulations, the thickness of bonding layer in the shorter pillar increased continuously with bonding time and pressure. In contrast, the thickness in standard pillars grew over time and eventually stabilized. During this, the bonding pressure posed negligible effects on the bonding layer thickness in standard pillars, and dislocations were generally concentrated near the bonding layer, serving as channels for Cu atom diffusion into the bonding layer.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.