Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL

A power-efficient, wide-band, programmable pseudo-differential ring-oscillator charge-pump phase-locked loop (CP-PLL) is proposed. The ring-VCO, characterized by its low power consumption and broadband, is achieved based on a feedforward pseudo-differential configuration. The linearity of ring-VCO is improved by using the source negative feedback topology. Through the rail-to-rail operatingamplifier clamping current source, the current matching accuracy is improved to realize a high-performance CP circuit. The results show that the output frequency range of the phase-locked loop is 0.6–6 GHz at a 1.2 V supply voltage, and the power consumption is 1.372 mW at 5 GHz with a lock-up time of 1.72 μs and RMS jitter of 9.3 ps. The power consumption is as low as 0.643 mW at 2.5 GHz and 1.067 mW at 4 GHz, and the final layout area is 0.00716 mm². The implemented CP-PLL can be used effectively in wireless RF communication system of NB-IoT and intelligent edge computing scenario.