A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC

In the emerging field of Computing-in-Memory (CIM), this study introduces a 28-nm CMOS-based Static Random Access Memory (SRAM) CIM macro capable of various computational modes, potentially offering a solution to the Von Neumann bottleneck. Beyond traditional SRAM read and write operations, to enhance the flexibility of the CIM macro, a 9T cell is proposed for performing AND, OR, and XNOR operations; a new capacitive weighting module is introduced to reduce the area of conventional ladder capacitors; and a redundant array-assisted Analog-to-Digital Converter (ADC) is proposed to improve linearity during ADC quantization. The proposed architecture can achieve multi-bit multiplication and accumulation (MAC), OR accumulation (ORA), and XNOR accumulation (XNORA). Simulated using a 28-nm CMOS process, the architecture demonstrated a minor standard deviation in BL voltage of 16.27 mV at the SS process corner, as evidenced by Monte Carlo simulation. At the TT process corner, the energy expenditure for MAC, XNORA, and ORA operations was 5.76, 5.85, and 5.82 fJ/op, respectively.