{"title":"基于机器学习的硅冷源场效应晶体管紧凑建模","authors":"Haoqing Xu;Weizhuo Gan;Shujin Guo;Shengli Zhang;Zhenhua Wu","doi":"10.1109/TNANO.2024.3442476","DOIUrl":null,"url":null,"abstract":"The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"615-621"},"PeriodicalIF":2.1000,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Machine Learning-Based Compact Modeling of Silicon Cold Source Field-Effect Transistors\",\"authors\":\"Haoqing Xu;Weizhuo Gan;Shujin Guo;Shengli Zhang;Zhenhua Wu\",\"doi\":\"10.1109/TNANO.2024.3442476\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.\",\"PeriodicalId\":449,\"journal\":{\"name\":\"IEEE Transactions on Nanotechnology\",\"volume\":\"23 \",\"pages\":\"615-621\"},\"PeriodicalIF\":2.1000,\"publicationDate\":\"2024-08-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Nanotechnology\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10634842/\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Nanotechnology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10634842/","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Machine Learning-Based Compact Modeling of Silicon Cold Source Field-Effect Transistors
The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.
期刊介绍:
The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.