Xiaodong Meng;Xing Li;Chi-Ying Tsui;Wing-Hung Ki;Weiqiang Liu
{"title":"用于无线供电植入式医疗设备的带分数电容自动调谐回路的 13.56-MHz 初级驱动器","authors":"Xiaodong Meng;Xing Li;Chi-Ying Tsui;Wing-Hung Ki;Weiqiang Liu","doi":"10.1109/JSSC.2024.3414159","DOIUrl":null,"url":null,"abstract":"A primary driver with a fractional capacitance (FC) auto-tuning loop (ATL) for wireless-powered biomedical devices is presented. The proposed ATL maintains the resonance of the primary LC tank against varying inductance over a wide range in real time. The analog ATL has a wide loop bandwidth and achieves phase locking within six cycles. The fractional capacitor is realized with a switch-controlled capacitor. By varying the turn-on time of the switch, the effective capacitance is changed, which tunes the resonant frequency of the primary LC tank. The primary driver is a full-bridge Class-D power amplifier (PA). High-side NMOS power switches are driven by bootstrap circuits. An adaptive offset controller is proposed to compensate for the delays of comparators to enhance tuning accuracy. The chip is fabricated using a 0.18-\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\nm bipolar-CMOS-DMOS (BCD) process, and the active area is 0.66 mm2. The system operates at 13.56 MHz and maintains both zero-voltage switching (ZVS) and zero-current switching (ZCS) in a steady state. The maximum PA output power is 200 mW, the measured tuning range is 31.5%, and the tuning error is 1.89 ns.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 10","pages":"3218-3231"},"PeriodicalIF":4.6000,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices\",\"authors\":\"Xiaodong Meng;Xing Li;Chi-Ying Tsui;Wing-Hung Ki;Weiqiang Liu\",\"doi\":\"10.1109/JSSC.2024.3414159\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A primary driver with a fractional capacitance (FC) auto-tuning loop (ATL) for wireless-powered biomedical devices is presented. The proposed ATL maintains the resonance of the primary LC tank against varying inductance over a wide range in real time. The analog ATL has a wide loop bandwidth and achieves phase locking within six cycles. The fractional capacitor is realized with a switch-controlled capacitor. By varying the turn-on time of the switch, the effective capacitance is changed, which tunes the resonant frequency of the primary LC tank. The primary driver is a full-bridge Class-D power amplifier (PA). High-side NMOS power switches are driven by bootstrap circuits. An adaptive offset controller is proposed to compensate for the delays of comparators to enhance tuning accuracy. The chip is fabricated using a 0.18-\\n<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>\\nm bipolar-CMOS-DMOS (BCD) process, and the active area is 0.66 mm2. The system operates at 13.56 MHz and maintains both zero-voltage switching (ZVS) and zero-current switching (ZCS) in a steady state. The maximum PA output power is 200 mW, the measured tuning range is 31.5%, and the tuning error is 1.89 ns.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"59 10\",\"pages\":\"3218-3231\"},\"PeriodicalIF\":4.6000,\"publicationDate\":\"2024-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10681594/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10681594/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices
A primary driver with a fractional capacitance (FC) auto-tuning loop (ATL) for wireless-powered biomedical devices is presented. The proposed ATL maintains the resonance of the primary LC tank against varying inductance over a wide range in real time. The analog ATL has a wide loop bandwidth and achieves phase locking within six cycles. The fractional capacitor is realized with a switch-controlled capacitor. By varying the turn-on time of the switch, the effective capacitance is changed, which tunes the resonant frequency of the primary LC tank. The primary driver is a full-bridge Class-D power amplifier (PA). High-side NMOS power switches are driven by bootstrap circuits. An adaptive offset controller is proposed to compensate for the delays of comparators to enhance tuning accuracy. The chip is fabricated using a 0.18-
$\mu $
m bipolar-CMOS-DMOS (BCD) process, and the active area is 0.66 mm2. The system operates at 13.56 MHz and maintains both zero-voltage switching (ZVS) and zero-current switching (ZCS) in a steady state. The maximum PA output power is 200 mW, the measured tuning range is 31.5%, and the tuning error is 1.89 ns.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.