Exploring popped-out phenomena in large-scale silicon ingot growth

Silicon wafers are essential for the semiconductor industry, providing the foundation for most integrated circuits. As demand for microelectronics grows, larger silicon wafers, have become crucial for increasing chip production and reducing manufacturing costs. However, the crystal separation phase during Czochralski (CZ) ingot growth is particularly challenging for larger ingots, often resulting in defects due to premature detachment (“popped-out” tails). This study investigates the popping-out stage of 18-inch ingots under varying heater power and ingot pull-out speed conditions. Photoluminescence (PL) imaging and a convolutional neural network (CNN) were used to analyze dislocation density in the silicon wafers. Results show that increasing the pull-out speed after detachment can significantly increase dislocation density, while pausing the ingot near the melt surface minimizes dislocations. Additionally, increasing heater power after detachment reduces dislocation density. The optimal condition for minimizing dislocation was found when heater power was doubled, and the ingot was paused near the melt surface for 30 min.