3D package thermal analysis and thermal optimization

3D packaging mainly uses TSVs (Through Silicon via) to vertically interconnect multiple chips, achieving the purpose of signal transmission and electrical connection. As a popular advanced packaging method, its research is of great significance. Although stacked chips can achieve stronger performance in smaller spaces, they can also cause a series of reliability issues, among which thermal stress and warping due to differences in the thermal expansion coefficients of materials can even lead to chip failure. Therefore, it is highly valuable to simulate and analyze the entire 3D packaging model.

In this study, the thermal stress and deformation of the whole three-dimensional package model were simulated by finite element analysis. The results showed that there were significant stress and deformation effects at the joint of the TSV structure at normal temperature, and the stress and deformation reached 209.99 MPa and 0.0018519 mm, respectively. After that, the temperature of the double-sided package system containing 3D package under electrothermal coupling conditions was optimized by heat dissipation design, which verified the ‘quantity first’ scheme of heat dissipation fins and reduced the temperature by 40 %.