Optimized design of multilayer embedded micro-fins for enhanced thermal management in three-dimensional stacked chips with heterogeneous heat sources

The increasing demand for high-density integration and superior performance in electronic devices has led to the adoption of three-dimensional stacking packaging technology. However, this advancement also brings forth complex thermal management challenges. To address these issues, this paper proposes an optimized design of multilayer embedded micro-fins within three-dimensional integrated chips. The placement of micro-fins between the chip layers aims to overcome the inefficiencies of heat transfer from heterogeneous heat sources. A comprehensive simulation model is developed to analyze the heat transfer properties of the proposed design, considering various factors such as interlayer micro-fin rates, shapes, layouts, and sizes. The results demonstrate a significant reduction of 15.2 % in peak temperature compared to the original structure, along with notable improvements in the overall heat transfer efficiency of the interlayer micro-fins, particularly at lower inlet Reynolds numbers. This research provides valuable theoretical insights for the thermal management of three-dimensional stacked chips, offering potential solutions to enhance heat dissipation and optimize chip performance.